of 23
All materials on our website are shared by users. If you have any questions about copyright issues, please report us to resolve them. We are always happy to assist you.

DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers

Category:

Shopping

Publish on:

Views: 2 | Pages: 23

Extension: PDF | Download: 0

Share
Description
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers GENERAL DESCRIPTION The DS89C430 and DS89C450 offer the highest performance available in 8051-compatible microcontrollers. They
Transcript
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers GENERAL DESCRIPTION The DS89C430 and DS89C450 offer the highest performance available in 8051-compatible microcontrollers. They feature newly designed processor cores that execute instructions up to 12 times faster than the original 8051 at the same crystal speed. Typical applications will experience a speed improvement up to 10x. At 1 million instructions per second (MIPS) per megahertz, the microcontrollers achieve 33 MIPS performance from a maximum 33MHz clock rate. The DS89C440 is a 32kB version of the DS89C450 that is no longer available. The DS89C450 can be used as a drop-in replacement. The Ultra-High-Speed Flash Microcontroller User s Guide should be used in conjunction with this data sheet. Download it at ORDERING INFORMATION PART FLASH MEMORY SIZE PIN-PACKAGE DS89C430-MNL 16kB 40 PDIP DS89C430-MNL+ 16kB 40 PDIP DS89C430-QNL 16kB 44 PLCC DS89C430-QNL+ 16kB 44 PLCC DS89C430-ENL 16kB 44 TQFP DS89C430-ENL+ 16kB 44 TQFP DS89C440-xxx Contact factory or replace with DS89C430 or DS89C450. DS89C450-MNL 64kB 40 PDIP DS89C450-MNL+ 64kB 40 PDIP DS89C450-QNL 64kB 44 PLCC DS89C450-QNL+ 64kB 44 PLCC DS89C450-ENL 64kB 44 TQFP DS89C450-ENL+ 64kB 44 TQFP + Denotes a lead-free/rohs-compliant device. Complete Selector Guide appears at end of data sheet. Pin Configurations appear at end of data sheet. FEATURES High-Speed 8051 Architecture One Clock-Per-Machine Cycle DC to 33MHz Operation Single Cycle Instruction in 30ns Optional Variable Length MOVX to Access Fast/Slow Peripherals Dual Data Pointers with Automatic Increment/Decrement and Toggle Select Supports Four Paged Memory-Access Modes On-Chip Memory 16kB/64kB Flash Memory In-Application Programmable In-System Programmable Through Serial Port 1kB SRAM for MOVX 80C52 Compatible 8051 Pin and Instruction Set Compatible Four Bidirectional, 8-Bit I/O Ports Three 16-Bit Timer Counters 256 Bytes Scratchpad RAM Power-Management Mode Programmable Clock Divider Automatic Hardware and Software Exit ROMSIZE Feature Selects Internal Program Memory Size from 0 to 64kB Allows Access to Entire External Memory Map Dynamically Adjustable by Software Peripheral Features Two Full-Duplex Serial Ports Programmable Watchdog Timer 13 Interrupt Sources (Six External) Five Levels of Interrupt Priority Power-Fail Reset Early Warning Power-Fail Interrupt Electromagnetic Interference (EMI) Reduction APPLICATIONS Data Logging Telephones White Goods HVAC Motor Control Magstripe Reader/Scanner Vending Gaming Equipment Building Energy Control and Management Programmable Logic Controllers Uninterruptible Power Supplies Building Security and Door Access Control Automotive Text Equipment Consumer Electronics Industrial Control and Automation Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: 1 of 49 REV: ABSOLUTE MAXIMUM RATINGS DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Voltage Range on Any Pin Relative to Ground -0.3V to (V CC + 0.5V) Voltage Range on V CC Relative to Ground..-0.3V to +6.0V Ambient Temperature Range (under bias) -40 C to +85 C Storage Temperature Range.-55 C to +125 C Soldering Temperature See IPC/JEDEC J-STD-020 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V CC = 4.5V to 5.5V, T O = -40 C to +85 C.) (Note 1) PARAMETER SYMBOL MIN TYP MAX UNITS Supply Voltage (Notes 2, 3) V CC V Power-Fail Warning (Notes 2, 4) V PFW V Reset Trip Point (Min Operating Voltage) (Notes 2, 3, 4) V RST V Supply Current, Active Mode (Note 5) I CC ma Supply Current, Idle Mode at 33MHz (Note 6) I IDLE ma Supply Current, Stop Mode, Bandgap Disabled (Note 7) I STOP µa Supply Current, Stop Mode, Bandgap Enabled (Note 7) I SPBG µa Input Low Level (Note 2) V IL V Input High Level (Note 2) V IH 2.0 V CC V Input High Level XTAL and RST (Note 2) V IH2 3.5 V CC V Output Low Voltage, Port 1 and 3 at I OL = 1.6mA (Note 2) V OL V Output Low Voltage, Port 0 and 2, ALE, PSEN at I OL = 3.2mA (Note 2) Output High Voltage, Port 1, 2, and 3, at I OH = -50µA (Notes 2, 8) V OL V V OH1 2.4 V Output High Voltage, Port 1, 2, and 3 at I OH = -1.5mA (Notes 2, 9) V OH2 2.4 V Output High Voltage, Port 0, 1, 2, ALE, PSEN, RD, WR in Bus Mode at I OH = -8mA (Notes 2, 10) V OH3 2.4 V Output High Voltage, RST at I OL = -0.4mA (Note 2, 11) V OH4 2.4 V Input Low Current, Port 1, 2, and 3 at 0.4V I IL -50 µa Transition Current from 1 to 0, Port 1, 2, and 3 at 2V (Note 12) I TL -650 µa Input Leakage Current, Port 0 in I/O Mode and EA (Note 13) I L µa Input Current, Port 0 in Bus Mode (Note 14) I L µa RST Pulldown Resistance (Note 13) R RST kω 2 of 48 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Specifications to -40 C are guaranteed by design and not production tested. All voltages are referenced to ground. The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that V RST (min) is specified below that point. This indicates that there is a range of voltages [(V MIN to V RST (min)] where the processor's operation is not guaranteed, but the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset. While the specifications for V PFW and V RST overlap, the design of the hardware makes it so this is not possible. Within the ranges given, there is guaranteed separation between these two voltages. Active current is measured with a 33MHz clock source driving XTAL1, V CC = RST = 5.5V. All other pins are disconnected. Idle mode current is measured with a 33MHz clock source driving XTAL1, V CC = 5.5V, RST at ground. All other pins are disconnected. Stop mode is measured with XTAL and RST grounded, V CC = 5.5V. All other pins are disconnected. RST = 5.5V. This condition mimics the operation of pins in I/O mode. During a 0-to-1 transition, a one shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition mode. When addressing external memory. Guaranteed by design. Note 12: Ports 1, 2, and 3 source transition current when pulled down externally. The current reaches its maximum at approximately 2V. Note 13: Note 14: RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode. This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at approximately 2V. 3 of 48 DS89C430/DS89C450 AC CHARACTERISTICS (V CC = 4.5V to 5.5V, T O = -40 C to +85 C.) (See Figure 1, Figure 2, and Figure 3.) PARAMETER SYMBOL 1-CYCLE PAGE MODE 1 2-CYCLE PAGE MODE 1 4-CYCLE PAGE MODE 1 PAGE MODE 2 NONPAGE MODE UNITS MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX System Clock External Oscillator (Note 15) System Clock External Crystal (Note 15) 1/t CLCL 0 1/t CLCL MHz ALE Pulse Width (Note 16) t LHLL 0.5t CLCL t STC3 t CLCL t STC3 2t CLCL t STC3 1.5t CLCL t STC3 1.5t CLCL t STC3 ns Port 0 Instruction Address Valid to ALE Low t AVLL t CLCL t CLCL - 3 ns Port 2 Instruction Address Valid to ALE Low t AVLL2 0.5t CLCL t CLCL t CLCL t CLCL - 4 t CLCL - 4 ns Port 0 Data AddressValid to ALE Low t AVLL3 t CLCL t CLCL - 3 ns t STC3 + t STC3 Program Address Hold After ALE Low Address Hold after ALE Low MOVX Write Address Hold after ALE Low MOVX Read t LLAX 0.5t CLCL t CLCL t CLCL - 8 1t CLCL t CLCL - 10 ns t LLAX2 0.5t CLCL t STC4 1.5t CLCL t STC4 2.5t CLCL t STC3 0.5t CLCL t STC2 0.5t CLCL t STC2 ns t LLAX3 0.5t CLCL t STC4 1.5t CLCL t STC4 2.5t CLCL t STC3 0.5t CLCL t STC3 0.5t CLCL t STC2 ns ALE Low to Valid Instruction In t LLIV 2t CLCL - 6 2t CLCL - 6 ns ALE Low to PSEN Low t LLPL 1.5t CLCL t CLCL - 2 ns PSEN Pulse Width for Program Fetch t PLPH t CLCL - 5 t CLCL - 5 2t CLCL - 5 t CLCL - 5 2t CLCL - 5 ns 4 of 48 AC CHARACTERISTICS (continued) (V CC = 4.5V to 5.5V, T O = -40 C to +85 C.) (See Figure 1, Figure 2, and Figure 3.) PARAMETER SYMBOL 1-CYCLE PAGE MODE 1 2-CYCLE PAGE MODE 1 4-CYCLE PAGE MODE 1 PAGE MODE 2 NONPAGE MODE UNITS MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX PSEN Low to Valid Instruction In t PLIV t CLCL - 20 t CLCL t CLCL - 20 t CLCL t CLCL - 20 ns Input Instruction Hold After PSEN t PXIX ns Input Instruction Float After PSEN t PXIZ t CLCL - 5 t CLCL - 5 ns Port 0 Address to Valid Instruction In t AVIV0 1.5t CLCL t CLCL - 22 ns Port 2 Address to Valid Instruction In t AVIV2 t CLCL t CLCL t CLCL t CLCL t CLCL - 20 ns PSEN Low to Port 0 Address Float RD Pulse Width (P3.7) (Note 16) WR Pulse Width (P3.6) (Note 16) t PLAZ 0 0 ns t RLRH t CLCL t STC1 t CLCL t STC1 2t CLCL t STC1 2t CLCL t STC1 2t CLCL t STC1 ns t WLWH t CLCL t STC1 t CLCL t STC1 2t CLCL t STC1 2t CLCL t STC1 2t CLCL t STC1 ns RD (P3.7) Low to Valid Data In (Note 16) t RLDV t CLCL - 18 t CLCL t CLCL t CLCL t CLCL - 18 ns + t STC1 + t STC1 + t STC1 + t STC1 + t STC1 Data Hold After RD (P3.7) t RHDX ns Data Float After RD (P3.7) t RHDZ t CLCL - 5 t CLCL - 5 ns MOVX ALE Low to Input Data Valid (Note 16) t LLDV 2t CLCL - 8 2t CLCL - 5 ns + t STC1 + t STC1 5 of 48 AC CHARACTERISTICS (continued) (V CC = 4.5V to 5.5V, T O = -40 C to +85 C.) (See Figure 1, Figure 2, and Figure 3.) PARAMETER SYMBOL 1-CYCLE PAGE MODE 1 2-CYCLE PAGE MODE 1 4-CYCLE PAGE MODE 1 PAGE MODE 2 NONPAGE MODE UNITS MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Port 0 Address to Valid Data In (Note 16) Port 2 Address to Valid Data In (Note 16) t AVDV0 t AVDV2 3t CLCL t CLCL - 20 ns + t STC1 + t STC1 t CLCL t CLCL - 3.5t CLCL - 3.0t CLCL t CLCL - ns + t STC t STC t STC1 + t STC t STC1 ALE Low to RD or WR Low (Note 16) t LLRL (t LLWL) 0.5t CLCL t STC2 0.5t CLCL t STC2 2t CLCL t STC2 2t CLCL t STC2 4t CLCL t STC2 4t CLCL t STC2 0.5t CLCL t STC2 0.5t CLCL t STC2 0.5t CLCL t STC2 0.5t CLCL t STC2 ns Port 0 Address Valid to RD or WR Low (Note 16) t AVRL0 (t AVWL0) + t STC2 t STC2 1.5t CLCL - 5 t CLCL ns Port 2 Address Valid to RD or WR Low (Note 16) Data Out Valid to WR Transition (Note 15) t AVRL2 (t AVWL2) 0 + t STC5-5 t QVWX t CLCL t CLCL - 5 t CLCL t CLCL - 5 ns + t STC5 + t STC5 t STC5 + t STC ns Data Hold After WR (Note 15) t WHQX t CLCL + t STC2-10 t CLCL + t STC2-10 t CLCL + t STC2-10 t CLCL + t STC2-10 t CLCL + t STC2-10 ns t RHLH RD or WR High to ALE High t STC2-2 t STC2 + 4 t STC2-2 t STC2 + 4 t STC2-2 t STC2 + 4 t STC2-2 t STC2 + 4 t STC2-2 t STC2 + 4 ns (Note 15) (t WHLH) Note: Specifications to -40 C are guaranteed by design and are not production tested. AC electrical characteristics assume 50% duty cycle for the oscillator and are not 100% tested, but are guaranteed by design. 6 of 48 DS89C430/DS89C450 Ultra-High-Speed Flash Micrcontrollers Note 15: The clock divide and crystal multiplier control bits in the PMR register determine the system clock frequency and the minimum/ maximum external clock speed. The term 1/t CLCL used in the AC Characteristics variable timing table is determined from the following table. The minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot exceed the rated speed of the device. In addition, the use of the crystal multiplier feature establishes a minimum external speed. Number of External Clock External Clock Speed 4X/2X CD1 CD0 Cycles per System Clock (1/t CLCL ) Min Max /4 5MHz 8.25MHz /2 10MHz 16.5MHz X 0 1 Reserved X See AC Characteristics See AC Characteristics X See AC Characteristics See AC Characteristics Note 16: External MOVX instruction times are dependent upon the setting of the MD2, MD1, and MD0 bits in the clock control register. The terms t STC1, t STC2, t STC3 used in the variable timing table above are calculated through the use of the table given below. MD2 MD1 MD0 MOVX Instruction Time t STC1 t STC2 t STC3 t STC4 t STC Machine Cycles 0 t CLCL 0 t CLCL 0 t CLCL 0 t CLCL 0 t CLCL Machine Cycles 2 t CLCL 1 t CLCL 0 t CLCL 0 t CLCL 1 t CLCL Machine Cycles 6 t CLCL 1 t CLCL 0 t CLCL 0 t CLCL 1 t CLCL Machine Cycles 10 t CLCL 1 t CLCL 0 t CLCL 0 t CLCL 1 t CLCL Machine Cycles 14 t CLCL 5 t CLCL 4 t CLCL 1 t CLCL 1 t CLCL Machine Cycles 18 t CLCL 5 t CLCL 4 t CLCL 1 t CLCL 1 t CLCL Machine Cycles 22 t CLCL 5 t CLCL 4 t CLCL 1 t CLCL 1 t CLCL Machine Cycles 26 t CLCL 5 t CLCL 4 t CLCL 1 t CLCL 1 t CLCL Note 17: Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load capacitance are dependent upon the frequency of the selected crystal. Figure 1. Nonpage Mode Timing XTAL1 ALE t CLCL tlhll t AVLL2 tavll3 t LLAX2 PSEN t AVLL tllax3 RD t LLPL t PXIX t PLPH tpliv trlrh tplaz t WHLH t LLWL WR Port 0 tlldv tavdv0 tavwl0 t LLIV trhdx t LLAX t AVIV0 trldv trhdz LSB MOVX LSB MOVX LSB DATA LSB OPCODE LSB t WLWH t WHQX t QVWX DATA t PXIZ t AVWL2 tavdv2 taviv2 Port 2 MSB MSB MSB MSB MSB 7 of 48 Figure 2. Page Mode 1 Timing XTAL1 ALE t CLCL tlhll PSEN tavll2 tllax3 tplph tllax t LLAX2 t WHLH RD tllwl WR trlrh trhdx tpxix t QVWX t WLWH t WHQX Port 0 t AVIV2 OPCODE MOVX MOVX trldv DATA tpliv OPCODE t AVWL2 DATA tavdv2 Port 2 LSB LSB LSB MSB LSB MSB LSB MSB LSB MSB Figure 3. Page Mode 2 Timing XTAL1 ALE t CLCL tlhll PSEN t AVLL t AVLL2 t PLPH tavll3 t LLAX2 RD WR t LLPL t PLIV t PXIX t LLIV t AVIV0 tllax3 trlrh tplaz tlldv trldv tavwl2 trhdx tavdv0 tavwl0 t WHLH t LLWL t WLWH t WHQX Port 0 LSB LSB LSB LSB LSB LSB t PXIZ trhdz t LLAX tavdv2 taviv2 t QVWX Port 2 MSB OPCODE MOVX MOVX MSB DATA MSB OPCODE MSB DATA 8 of 48 EXTERNAL CLOCK CHARACTERISTICS (V CC = 4.5V to 5.5V, T O = -40 C to +85 C.) DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers PARAMETER SYMBOL MIN MAX UNITS Clock High Time t CHCX 10 ns Clock Low Time t CLCX 10 ns Clock Rise Time t CLCH 5 ns Clock Fall Time t CHCL 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS (V CC = 4.5V to 5.5V, T O = -40 C to +85 C.) (Figure 4) PARAMETER SYMBOL CONDITIONS 33MHz VARIABLE MIN MAX MIN MAX UNITS SM2 = t CLCL ns Clock Cycle Time t XLXL SM2 = t CLCL ns Output Data Setup to Clock Rising t QVXH SM2 = t CLCL ns SM2 = t CLCL - 10 ns Output Data Hold to Clock Rising t XHQX SM2 = t CLCL - 10 ns SM2 = 1 20 t CLCL Input Data Hold After Clock Rising t XHDX SM2 = ns SM2 = Clock Rising Edge to Input Data Valid SM2 = t CLCL ns t XHDV SM2 = t CLCL - 50 ns Note: SM2 is the serial port 0 mode bit 2. When serial port 0 is operating in mode 0 (SM0 = SM1 = 0), SM2 determines the number of crystal clocks in a serial port clock cycle. 9 of 48 Figure 4. Serial Port Timing SERIAL PORT (SYNCHRONOUS MODE) SM2 = 1 TDX CLOCK = XTAL FREQ/4 ALE PSEN WRITE TO SBUF tqvxh txhqx RXD DATA OUT D0 DI D2 D3 D4 D5 D6 D7 TXD CLOCK TRANSMIT TI txlxl WRITE TO SCON TO CLEAR RI RXD DATA IN TXD CLOCK D0 DI D2 D3 D4 D5 D6 D7 RECEIVE R1 txhdv txhdx SERIAL PORT (SYNCHRONOUS MODE) SM2 = 0 TDX CLOCK = XTAL FREQ/12 ALE PSEN WRITE TO SBUF 1/(XTAL FREQ/12) RXD DATA OUT TXD CLOCK D0 DI D6 D7 TRANSMIT TI WRITE TXD CLOCK TO SCON TO CLEAR RI RXD DATA IN TXD CLOCK R1 D0 DI D6 D7 RECEIVE 10 of 48 POWER-CYCLE TIMING CHARACTERISTICS (V CC = 4.5V to 5.5V, T O = -40 C to +85 C.) DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers PARAMETER SYMBOL MIN TYP MAX UNITS Crystal Startup Time (Note 18) t CSU 8 ms Power-On Reset Delay (Note 19) t POR 65,536 t CLCL Note 18: Startup time for a crystal varies with load capacitance and manufacturer. The time shown is for an MHz crystal manufactured by Fox Electronics. Note 19: Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin meets the V IH2 criteria. At 33MHz, this time is 1.99ms. FLASH MEMORY PROGRAMMING CHARACTERISTICS (V CC = 4.5V to 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS Data Retention t DR 100 years Write/Erase Endurance t ENDURE 10,000 cycles Program/Time t PROG 40 µs Erase Time t ERASE 4 ms 11 of 48 PIN DESCRIPTION PIN PDIP PLCC TQFP NAME FUNCTION 40 12, 44 6, 38 V CC +5V 20 1, 22, 23, 34 16, 17, 28, 39 GND RST XTAL XTAL PSEN ALE/PROG P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) Logic Ground External Reset. The RST input pin is bidirectional and contains a Schmitt Trigger to recognize external active-high reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wire-ored external reset sources. An RC is not required for power-up, as the device provides this function internally. Crystal Oscillators. These pins provide support for fundamental-mode parallel-resonant AT-cut crystals. XTAL1 also acts as an input if there is an external clock source in place of a crystal. XTAL2 serves as the output of the crystal amplifier. Program Store Enable. This signal is commonly connected to optional external program memory as a chip enable. PSEN provides an active-low pulse and is driven high when external program memory is not being accessed. In one-cycle page mode 1, PSEN remains low for consecutive page hits. Address Latch Enable. This signal functions as a clock to latch the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external 373-family transparent latch. In default mode, ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. In page mode, the ALE pulse width is altered according to the page mode selection. In traditional 8051 mode, ALE is high when using the EMI reduction mode and during a reset condition. ALE can be enabled by writing ALEON = 1 (PMR.2). Note that ALE operates independently of ALEON during external memory accesses. As an alternate mode, this pin (PROG) is used to execute the parallel program function. Port 0 (AD0 AD7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an alternate function, Port 0 can function as the multiplexed address/data bus to access offchip memory. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls to logic 0, the port transitions to a bidirectional data bus. This bus is used to read external program memory and read/write external RAM or peripherals. When used as a memory bus, the port provides weak pullups for logic 1 outputs. The reset condition of port 0 is tri-state. Pullup resistors are required only when using port 0 as an I/O port. 12 of 48 PIN DESCRIPTION (continued) PIN PDIP PLCC TQFP NAME P P P P P P P P P2.0 (A8) P2.1 (A9) P2.2 (A10) P2.3 (A11) P2.4 (A12) P2.5 (A13) P2.6 (A14) P2.7 (A15) P P P P P P P P EA FUNCTION Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for timer 2 I/O, new external interrupts, and new serial port 1. The reset condition of port 1 is with all bits at logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input state, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C430/DS89C450 activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes the output high (and input) state. The alternate functions of port 1 are as follows: PORT ALTERNATE FUNCTION P1.0 T2 External I/O for Timer/Counter2 P1.1 T2EX Timer 2 Capture/Reload Trigger P1.2 RXD1
Similar documents
View more...
Search Related
We Need Your Support
Thank you for visiting our website and your interest in our free products and services. We are nonprofit website to share and download documents. To the running of this website, we need your help to support us.

Thanks to everyone for your continued support.

No, Thanks